The present invention relates to a process for fabricating and programming ROM type memory cells, made in MOS or CMOS technology with an LDD (a commonly used acronym of Lightly Doped Drain), source and/or drain graded diffusion. Programming is effected by making permanently nonconducting all the "programmed" cells of a ROM matrix having a com-mon-source configuration (commonly known as a "NOR-type" ROM).
ROM memories are commonly used in microprocessor-based systems made in MOS or CMOS technology, and their programming with a certain content of information corresponding to the specific application takes place during the fabrication process of the integrated circuits containing ROM memory sections. For this reason, from a point of view of the management of customer's orders and production, it is advantageous to be able to program the ROM memories as late as possible in the device fabrication process. The single ROM memory cells are generally composed of an n-channel or a p-channel transistor, while ever more often the read circuitry of the memory cell matrix, as well as other circuits integrated on the same chip, are made in CMOS technology, for obvious reasons of reducing power consumption.
The programming of ROM memories by purposely modifying the mask used for defining the active areas of the cells which will exclude altogether the formation of a cell in certain preestablished locations of the matrix causing the formation of a thick field oxide layer in those locations instead of the formation of a thin gate oxide layer, remains a commonly used technique. However this approach requires programming to be effected in a relatively initial phase of the fabrication process of integrated circuits and therefore other methods of programming which may be carried out during later steps of the fabrication process are favored. According to another known approach, the programming of n-channel memory cells is effected by implanting boron through the apertures of dedicated programming mask in an amount sufficient to raise the threshold voltage of the cells of the matrix to be "programmed".
Another known solution consists in implanting boron exclusively in the source zone of the cells to be programmed, and by thereafter diffusing it under the gate structure. In this way, it is possible to increase the threshold voltage above the supply voltage without significantly lowering the breakdown voltage because the latter is influenced by the doping level of the channel near the drain junction of the cells. Nevertheless, also this process is not always satisfactory and in particular it is inapplicable to VLSI devices, having a common-source type of architecture of the ROM memory matrix.
According to a process described in a prior Italian Patent No. 1,217,372 of the same Applicant of the present application, which is hereby incorporated by reference, the programming of the cells of a ROM memory may be advantageously effected by the use of the same mask which is used for implanting source and drain junctions, by masking the source and/or drain areas adjacent to an already formed gate structure of the matrix's cells to be programmed, thus obtaining a decoupling between the gate and the source and drain regions, by virtue of the backing off of the latter from the respective gate structure.
All these known programming processes have been used primarily with memory cells having a standard structure, i.e. a structure which does not contemplate the formation of source and drain junctions with a graded diffusion profile obtained through two distinct steps of implantation carried out in self-alignment with the gate structure. (Typically, as mentioned above, such LDD structures are fabricated using a first relatively lighter implantation immediately after having defined the gate structures, and a second relatively heavier implantation after having formed so-called dielectric spacers along the sides of the gate structure; but this sequence can be varied.) On the other hand, memory cells with junctions having a graded diffusion profile ensure a better long term reliability and generally this technique is being widely used in high density integration processes for making highly reliable MOS transistors with improved electrical parameters, notably in the circuitry which is normally integrated region on the same chip together with a ROM memory matrix.
The present invention advantageously provides a fabrication and programming process for a ROM memory matrix with cells having junctions with a graded diffusion (LDD), which is remarkably simple to implement and which permits both n-channel and p-channel LDD-type transistors to be used in the ancillary and external circuitry without any requirement for additional masks.
Basically, the programming process of the invention consists of implanting an area defined by a noncritical mask and in a self-alignment condition in relation to the edge of a preformed gate structure, with a second dopant of a type suitable to produce in the semiconducting substrate a type of conductivity opposite to the one which is produced by a first dopant which is implanted on the same area when performing a first LDD implantation of the drain regions of all the cells. Such an implantation of said second dopant is performed in an amount sufficient to completely compensate and invert the type of conductivity produced by said first dopant in a portion of the drain region of the cell which is immediately adjacent to the gate structure of a cell to be programmed. Of course the attributes "first" and "second" of the dopants do not imply a specific order of implantation, and in fact the order may be inverted.
Normally, in the most common case of n-channel cells, a first n-type LDD implantation of the cells drain area, typically using phosphorus, is "compensated" and "inverted," in cells to be programmed by a programming (LDD) boron implantation also effected in self-alignment to the preformed gate structure, in a portion of the drain area of the cell close to the gate structure. According to a first embodiment of the invention, the programming implantation step (e.g. Boron implant) may be performed before proceeding to form dielectric spacers on the sides of the gate structure and before performing a second (LDD) implantation carried out in self-alignment to the gate structure provided with lateral spacers, in the source area, with a dopant capable of enhancing an n-type conductivity, e.g. with phosphorus itself or more commonly with arsenic, while masking during this subsequent implantation the drain area of all the memory cells of the matrix by using a purposely modified (LDD) mask. In integrated circuits containing both n-channel and p-channel transistors, i.e. in a CMOS process, the programming mask used for the compensating-inverting boron implantation may conveniently be the same mask which is used for effecting a boron LDD implantation on drain and source areas of p-channel transistors of ancillary circuitry external to the memory matrix, actually modified in accordance with the data to be permanently recorded in the matrix of memory cells for the specific application.
The second step of implantation of the source and drain areas of the n-channel devices of the external circuitry with arsenic or phosphorus, in self-alignment with the gate structures provided with spacers, may then be effected by modifying the mask used for this purpose in the area occupied by the matrix of memory cells, so as to mask the drain areas of all the memory cells of the matrix. In view of the fact that the external reading circuitry, as well as other systems, integrated in the same memory device, commonly use CMOS structures (i.e. n-channel transistors as well as p-channel transistors), the fabrication process of the invention may be seen to be extremely advantageous by not requiring any additional process step. Of course, the same process of the invention may be used also for programming ROM memories with n-channel LDD cells in devices containing only n-channel LDD transistors. In this case, the repeated n-type dopant implantation would take place normally without using a mask and therefore it is necessary to use a dedicated programming mask for defining, within the areas of the matrix's cells to be programmed, a portion of the drain area defined by the mask wherein boron must be implanted in an amount sufficient to invert the type of conductivity which is produced in the semiconductor by an n-type dopant (typically phosphorus or arsenic) during a first LDD implantation step. Of course, the same process is valid also in case of channel ROM cells, by inverting the row of the dopants.
The process of the invention may also be implemented in an alternative form by effecting the programming implantation at a more advanced stage of the fabrication process of the devices, by using a high energy implantation process. In this case it is necessary to use a dedicated programming mask and a dedicated programming implantation step, however the additional cost is amply balanced by the great advantage of permitting the programming of the ROM memory matrix in a far more advanced step of the fabrication process of the integrated circuits. In practice, the programming implantation may be effected by implanting boron at high kinetic energy through the thickness of an intermediate dielectric isolation layer which is normally deposited after having completed the formation of the junctions in the semiconducting substrate and, desirably, after having "opened" the contacts and preferably before depositing the first metal layer.
The structure of the single memory cells of the invention has a source junction with a graded diffusion profile (LDD) while the drain junction has a configuration that comprises a drain region having a relatively light doping level, as obtained through a first LDD implantation and diffusion, because in the drain areas of the memory cells a subsequent implantation after having formed dielectric spacers on the sides of the gate structure is not performed. In practice the drain region of the memory cells retains a relatively low intrinsic doping level but this has been found not to modify in an appreciable way the electrical performances of the cells. This because of two factors, the first is due to the fact that the resistance of the lightly doped drain region is in any case substantially low in respect to the series resistance of the transistor, the second is due to the fact that by effecting a contact-area implantation and diffusion through the drain contact apertures before depositing the metal, the residual lateral extension of the low doping drain region is extremely small and therefore the ohmic drop through the drain region of the cells is in practice negligible.